//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// M8051W/EW Bit-slice ALU Element
// 
// $Log: m3s001dy.v,v $
// Revision 1.6  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.2  2001/10/31
// First parsable verilog for EW
//
// Revision 1.1.1.1  2001/07/17
// Re-imported E-Warp from Farnham filesystem
//
// Revision 1.5  2000/10/24
// Multiplier rewritten to improve power consumption.
// Code changes for Leonardo (ECN01372).
// Code changes for formal verification tools (ECN01410).
// MOVX @Ri page address controllable from PORT2I if I/O ports ommitted (ECN01387).
//
// Revision 1.4  2000/02/05
// Name change repercussions
//
// Revision 1.3  1999/11/30
// More debug changes.
//
// Revision 1.2  1999/11/08
// VerilogXL syntax corrections
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
// Revision 1.1  1999/10/22
// Initial revision
//
////////////////////////////////////////////////////////////////////////////////

`include "m8051w_cfg.v"

module m3s001dy (P, CO, ALU_CON, A, B);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //

  output P;
  output CO;
  input  [5:0] ALU_CON;
  input  A;
  input  B;

  reg   CO;
  reg   P;

//*********************************************************************
// Notes
// SINGLE BIT ALU ELEMENT. ALU_CON CARRIES THE OPERATION CODE
// P IS THE PRODUCT.
// CO IS THE CARRY/BORROW OUT
//
// OPERATION CODE
//      0 1 2 3 4 5 | P OUTPUT
//      ------------+-------------
//      0 0 0 0 X X | 0
//      1 1 0 0 X X | not A
//      0 1 1 1 X X | A or B
//      0 1 0 1 X X | A exor B
//      0 0 1 1 X X | A
//      0 0 1 0 X X | A and B
//      1 0 1 0 X X | A - B
//      0 1 1 0 X X | B
//      X X X X 1 X | Enable CARRY
//      X X X X X 1 | Enable BORROW
//
//*********************************************************************

  always @ (A or B or ALU_CON)
  begin : p_alu_slice
    P  <=   ~A && ~B && ALU_CON[0] || ~A &&  B && ALU_CON[1]		
          || A &&  B && ALU_CON[2] ||  A && ~B && ALU_CON[3];		
    CO <=    A &&  B && ALU_CON[4] ||  A && ~B && ALU_CON[5];
  end		

endmodule
